ALVIN W. STRONG, PhD, is retired from IBM in Essex Junction,
Vermont. He holds nineteen patents, has authored or coauthored a
number of papers, and is a member of the IEEE and chair of the
JEDEC 14.2 standards subcommittee.

ERNEST Y. WU, PhD, is a Senior Technical Staff Member at
Semiconductor Research and Development Center (SRDC) in the IBM
System and Technology Group. He has authored or coauthored more
than 100 technical or conference papers. His research interests
include dielectric/device reliability and electronic physics.

ROLF-PETER VOLLERTSEN, PhD, is a Principal for
Reliability Methodology at Infineon Technologies AG in Munich,
Germany, where he is responsible for methods and test structures
for fast Wafer Level Reliability monitoring and the implementation
of fast WLR methods.

JORDI SUNE, PhD, is Professor of Electronics Engineering
at the Universitat Aut¿noma de Barcelona, Spain. He is Senior
Member of the IEEE and has coauthored over 150 publications on
oxide reliability and electron devices. His research interests are
in gate oxide physics, reliability statistics, and modeling of
nanometer-scale electron devices.

GIUSEPPE LaROSA, PhD, is Project Leader of the FEOL
technology reliability qualification activities for the development
of advanced SOI Logic and eDRAM technologies at IBM, where he is
responsible for the implementation and development of
state-of-the-art NBTI stress and test methodologies.

TIMOTHY D. SULLIVAN, PhD, is Team Leader for
metallization reliability at IBM's Essex Junction facility. The
author of numerous technical papers and tutorials, he holds
thirteen patents with several more pending.

STEWART E. RAUCH, III, PhD, is currently a Senior
Technical Staff Member at the IBM SRDC in New York, where he
specializes in hot carrier and NBTI reliability of state-of-the-art
CMOS devices. He is the author of numerous technical papers and
tutorials and holds five patents.